1. Technical Field of the Present Invention
The present invention generally relates to the semiconductors, and more specifically to the estimation of yield using critical area analysis.
2. Description of Related Art
The fabrication of Integrated Circuits (ICs) has become an extremely complex and expensive process that involves thousands of operations such as selectively implanting impurities into, and applying conductive and insulative layers onto, a semiconductor substrate. The ICs are manufactured as a group on a wafer that is eventually diced into individual ICs.
The number of good ICs on a wafer is referred to as yield and is influenced by any number of manufacturing processes each of which can introduce a defect. Defects are typically caused by foreign particles, minute scratches and other imperfections introduced during photoresist, photomask and diffusion operations.
The pricing of the ICs for a particular technology is often based upon the complexity of the design and the anticipated yield. In addition, the capacity of the manufacturing facility is also based on an anticipated yield for all work in progress. It has, therefore, become critical to accurately predict yield for a particular design in a manufacturing process.
Circuit designs often include redundant elements for specified portions so that yield can be increased. Current yield prediction tools treat both the redundant and non-redundant elements equally when performing their analysis. Unfortunately, this treatment can result in yield predictions that are inaccurate because they do not consider that faults in redundant features will not impact yield to the same extent as non-redundant features.
It would, therefore, be a distinct advantage to have a method, system, and computer program product that would treat redundant and non-redundant elements differently during yield estimations so that yield can be more accurately predicted.